NAMC-SDH

NAMC-SDH: AMC Line Interface between SDH/SONET and TDM

Interface between STM-1/STM-4 and TDM standards such as E1/T1 or E3/T3

The NAMC-SDH is a telecommunication interface board in the Advanced Mezzanine Card (AdvancedMC or AMC) form factor, targeting telecom applications dealing with Synchronous Digital Hierarchy (SDH) in SDH/SONET networks.

Add/drop multiplexer to interface between SDH/SONET and classic TDM
Equipped with the TEMUX336 add/drop multiplexer/demultiplexer chipset from PMC Sierra, the NAMC-SDH is an ideal single board platform to interface between the frame oriented STM-1 or STM-4 SDH/SONET networks and classic TDM (Time Division Multiplex) standards as E1/T1 or E3/T3.

The TEMUX336 implements 252 E1 or 336 T1 framers as well as four OC-3/STM-1 or two OC-4/STM-4 (one backup) interfaces. What's more, the TEMUX336 provides an ESSI link for redundant/fail-over operation which is available at AMC port 16, making it suitable for applications based on the Advanced Telecommunications Computing Architecture (AdvancedTCA or ATCA). Thus, using the NAMC-SDH not only provides redundancy at optical port level but also across the board level.

Xilinx Kintex-7 for data pre-processing, manipulation or filtering
The on-board Xilinx Kintex-7 FPGA provides the NAMC-SDH with a scalable and flexible but powerful onboard data engine, allowing for pre-processing and/or filtering. The Kintex-7 FPGA also allows the NAMC-SDH to seamlessly interface between the TDM domain and the Ethernet domain as needed by, for example, VoIP applications. By default, the NAMC-SDH is supplied with an XC7K325T, but other XC7K variants can be supplied on request.

The Kintex-7 FPGA is almost entirely available for custom use and is by default equipped with a standard image that implements an I-TDM engine, which is fully compliant with the PICMG I-TDM specifications SFP.1, and a Time Slot Interchanger (TSI). In order to allow for sophisticated solutions, you can specify different kinds of external memories connected to the FPGA on the NAMC-SDH, for example two 72 Mbit QDR2+ SRAMs or one 2 GB DDR3 SRAM (default), thus providing sufficient memory resources for the full channel count.

Time Slot Interchanger (TSI) and HDLC Controller
An optional function block for the FPGA implements an HDLC controller, which offers a total capacity of 2000 x 64 kbit/s (2000 x DS0 bandwidth) per direction. It can be configured to handle up to 2000 separate 64 kbit/s channels, or to combine each up to 31 of the 64 kbit/s time-slots to super-channels. The TSI Block is used to either cross-connect a time-slot directly from Rx to Tx, to connect a time-slot to the ITDM controller, or to connect one or multiple of them to a channel of the HDLC controller.

Optical interfaces, multiple 1GbE Ethernet Interfaces and fat pipe support
The NAMC-SDH provides four optical interfaces on the front panel (four SFP connectors) which can be equipped with SFP transceivers to achieve up to four STM-1 or two STM-4 interfaces. At the AMC connector, the NAMC-SDH offers four 1GbE interfaces at AMC ports 0, 1, 4 and 8. This allows the board to operate in redundant setups as well as to select whether data transfer resides in the AMC Common-Option region (port 0 / 1) or in the Fat-Pipe region (port 4 / 8).

When operating in the Fat-Pipe region the NAMC-SDH will typically connect to a 10G Ethernet switch (e.g. NAT-MCH) configured to Gigabit transmission mode for the respective port. In addition to the multiple Ethernet interfaces the NAMC-SDH is prepared for optional Fat Pipe support (i.e. XAUI or SRIO) at AMC ports 4-7.

Clock domains
The NAMC-SDH is equipped with a STRATUM-3 PLL, which allows it to operate as a clock master or a clock slave. Thus, the NAMC-SDH can derive the network clock from one of the line interface ports and supply a synchronized clock to all other AMCs in the system or derive the system clock from the AMC backplane connector and supply a synchronized clock to all line interfaces. Alternatively, when set to free-running mode the PLL can be used to operate the NAMC-SDH as a clock generator.  Moreover, the PLL has hold-over capabilities.

Configuration
Besides the payload data, all configuration and management data going to and coming from the NAMC-SDH board is transmitted via Ethernet. Therefore, a control interface within the FPGA is able to handle Ethernet frames carrying a special protocol based upon regular Layer2 Ethernet. This handles memory-mapped accesses on the board internal memory map, covering both FPGA internal blocks as well as external devices like the TEMUX336. This allows the controlling host to reside inside or outside the ATCA or MicroTCA system, ideal for distributed applications.

Targeted applications
Typical applications for the NAMC-SDH are for example, add/drop or terminal mulitplexers or any other application in optical OC-3/STM-1 or OC-12/STM-4 and SDH/SONET environments, such as SS7, ISDN or 3G/3.5G mobile applications with a need for an onboard data manipulation or a filter engine.

Family of products
The NAMC-SDH belongs to the SDH/SONET family of products, which consists of
 



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Optical Interface on front panel
  • Four SFP receptacles for either
    • Four 155Mbps OC-3/STM-1 interfaces, or
    • Two 622Mbps OC-12/STM-4 interfaces (one backup)


VT/TU Access

  • SDH framers connected to TEMUX336 add/drop multiplex/demultiplex chipset
  • Access to VT/TU tributary unit groups within the VC3, VC4 and VC4-4c virtual containers
  • Extract/insert of up to 252 E1 or 336 T1 streams including respective clocking information contained in a single STM-1 or STM-4 SDH frame
  • Supported mappings: VT1.5/VT-2 or TU-11/TU-12 to VC3/VC4/VC4-4c or STM4/STM4c

T1/J1/E1 Access
  • 252 E1 or 336 T1 framers
  • Individual Rx/Tx, CLK and SYNC signals
  • T1 framing standards: SF, SLC-96 and ESF
  • E1 framing standards: G.704 and G.706 (CRC-4 multiframe)
  • Full jitter attenuation

TDM and I-TDM Interface
  • E1/T1 framer interfaces to the on-board timeslot interchanger (TSI)
  • Incorporated TSI and TDM-to-I-TDM bridge (on-board FPGA)
  • Flexible routing and multicasting of 64kbps timeslots between the various E1/T1 streams (TSI)
  • TDM-to-I-TDM bridge converts the TDM oriented bit stream into Ethernet packets and vice versa
  • Ethernet packets are sent and received via either the AMC ports 0, 1, 4 and 8 (selectable)

Control and Configuration
  • Via Ethernet on either AMC port 0 or 1
Form factor
  • AMC: single width, mid or full size

Add/drop multiplexer, E1/T1 and SDH interfaces
  • PMC TEMUX336
  • 252 E1or 336 T1 framers
  • 4 OC-3/STM-1 or 2 OC-12/STM-4 interfaces
  • access possible down to single DS0 level

FPGA
  • XLINX Kintex-7
    • Default assembly: XC7K325T
    • Other XC7K derivates on request
  • Available for custom use
  • Optionally featuring
    • SDH-Interface
    • Time-Slot-Interchanger (TSI)
    • iTDM-Controller
    • HDLC-Controller (optional)
    • Control Interface
    • Ethernet Interface(s)

Memory
  • External memory for FPGA
    • Either two 72Mbit QDR2+ SRAMs
    • Or one 2GB DDR3 SRAM (default)

Front Panel Elements
  • Four SFP connectors to host
    • Either 4x OC-3/STM-1 SFP transceivers
    • Or 2x OC-12/STM-4 SFP transceivers
  • Four bi-color link LEDs
  • Standard AMC LEDs

Backplane interfaces
  • 4x Gigabit Ethernet interfaces at AMC ports 0, 1, 4, 8
  • optional fat pipe (XAUI or SRIO) at AMC ports 4-7
  • ESSI for redundant/failover operation at AMC port 12
  I-TDM
  • Via Gigabit Ethernet at AMC ports 0, 1, 4, 8
  • PICMG SFP.1 Rev 1.0

Standard Compliance
  • PICMG AMC.0 Rev. 2.0
  • PICMG SFP.0 Rev. 1.0 (System Fabric Plane Format)
  • PICMG SFP.1 Rev. 1.0 (Internal TDM)
  • PICMG HPM.0 (Hardware Platform Management)
  • IPMI Specification v2.0 Rev. 1.0
  • PICMG µTCA.0 Rev. 1.0


Operating System Support

  • Host driver for Ethernet Control Interface, supported O/S:
    • LINUX
    • OK-1


Power Consumption

  • 3.3V, 12V, 20W typ.


Environmental

  • Temperature (operating): 0ºC to +50ºC with forced air cooling
  • Temperature (storage): -40ºC to +85ºC
  • Relative Humidity: 10% to 90% at +55ºC (non-condensing)

Applications
  • High density multiplexers, multi-service switches, edge routers and digital modems
  • Access devices
  • SONET/SDH add drop and terminal multiplexers
  • Optical access equipment
  • Digital access cross-connect systems
  • Data monitoring systems
  • Network test equipment



Title
Description
Format
Size
Rev #
Date Last Modified
namc_sdh_ds Data Sheet pdf - - -
namc_sdh_man_hw Hardware Manual pdf 894 KB 1.1 31-05-2015



NAMC-STM1/4 block diagram


Product Code: NAMC-SDH - [Option F]-[Option M]-[Option S]-[Option N]

Option
Value
Description
Comment
F -0
-1
type of Kintex-7 FPGA 0 = XC7K325T
1 = XC7K160T
(other types on request)
M -0
-1
-2
external memory for FPGA 0 = no external memory
1 = one 72Mbit QDR2+ SRAM
2 = two 72Mbit QDR2+ SRAMs
S -0
-1
-2
type of SFP transceiver (SDH level) 0 = no transceiver
1 = STM1 (OC-3)
2 = STM4 (OC-12)
N -0
-1
-2
-3
-4
number of transceivers 0 = no transceiver
1 = one STM1 or STM4 transceiver
2 = two STM1 or STM4 transceivers
3 = three STM1 transceivers
4 = four STM1 transceivers




Software:

Title
Description
Rev #
Date Last Modified
DRV-NAMC-SDH-LINUX-PRJ Project License Linux Driver (Ethernet Control Interface) for NAMC-SDH  1.0 29-07-2014