NAT-MCH-PHYS80: MCH for Physics or MTCA.4 applications with optical & copper PCIe uplinks

MicroTCA Carrier Hub for management and switching

The NAT-MCH-PHYS80 addresses the requirements for higher bandwidth to both AMCs and the rear transition slot of the MCH as well as for optical and copper uplinks in PCIe based MTCA.4 systems, targeting large control and data acquisition applications such as high energy physics research institutions.

Based on the NAT-MCH-M4, our double-wide MCH base board for MicroTCA.4 systems, combined with the NAT-MCH-CLK-PHYS, our special low latency and low jitter clock module, this new PCIe hub module is the most powerful single-slot solution for management and switching that is available for MTCA.4.

Special low jitter, low latency clock module for Physics applications
The NAT-MCH-CLK-PHYS clock module is specially designed for Physics applications, providing a very low-jitter and low-latency clock at CLK1 and CLK2 and a fixed mean 100MHZ PCIe clock. The NAT-MCH-PHYS80 is capable of sourcing an external clock from, or delivering an internal clock to, two SMA inputs or outputs on the front panel. This allows installations of many MTCA systems to be synchronized to a central clock source in a very elegant and easy-to-use way.

PCIe Gen3 switch providing optical or copper uplinks and virtual clustering
The PCIe hub module provides an 80-port PCIe Gen3 switch that allows each of the 12 Advanced Mezzanine Cards (AdvancedMCs or AMCs) in a MicroTCA.4 system to be connected by a x4 link and additionally provides either two x8 or one x16 optional optical PCIe uplink(s) to external high performance servers or other MTCA.4 systems (NAT-MCH-PHYS80-UPLNK only) and a x16 link to the rear transition module. If no optical but coppper uplinks are required, the NAT-MCH-PHYS80 can be used together with the NAT-MCH-RTM-UPLNK rear transition module, which then provides one x16 copper uplink on the front panel of the rear transition module. The PCIe switch also accomodates higher bandwidths, i.e. x8 or x16, to a reduced number of AMC slots if the backplane provides appropriate connectivity. Finally, the PCIe switch provides the ability to establish up to six virtual PCIe clusters and assign the AMC slots to these.

Rear Transition Module with Intel® dual or quad Core™ i7
When used together with its Rear Transition Module (RTM) NAT-MCH-RTM-RF the NAT-MCH-PHYS80 also connects the optional dual- or quad-core Intel® Core™ i7 Ivy Bridge ComExpress module with a x16 link to the PCIe Gen3 switch. As the fully user-accessible quad-core Intel Core i7 on the NAT-MCH-RTM-RF can act as a PCIe root complex, this x16 PCIe link overcomes the bottle neck between the root complex and many PCIe based I/O payload AMCs, which in most MTCA.4 systems are connected by a x4 link only.

Single slot solution for system management and PCIe root complex
Like the NAT-MCH-PHYS the NAT-MCH-PHYS80 can be equipped with SSD storage that will then turn the combination of NAT-MCH-PHYS80 and NAT-MCH-RTM-RF-COMex-i7Q into a true single-slot fully user-accessible root complex at PCIe Gen3 speed.

Management for Low Level RF (LLRF) backplane
The purpose of the LLRF backplane, which in MTCA.4 can optionally be mounted behind the standard MTCA.4 backplane, is to distribute high-precision RF and CLK signals as commonly used in particle physics among extended Rear Transition Modules (eRTM), as well as to supply additional managed power to these eRTMs and standard RTMs (uRTM or μRTM) using an additional connector to the LLRF backplane. By using the NAT-MCH-RTM-RF RTM, which also connects the management for the LLRF backplane to the MCH management, the NAT-MCH-PHYS80 can manage both eRTMs as well as uRTMs and the additional power modules (RTM-PM) connected to the LLRF backplane.

Redundant Environments
The NAT-MCH-PHYS80 fully supports redundant management and power environments. Frequent exchange of the internal databases with the secondary MCH and a heart beat mechanism ensure an immediate switch-over from the primary to the secondary MCH whenever it becomes necessary (PCIe fat pipe switch over may require additional precautions). The NAT-MCH-PHYS80 can handle up to four power modules, such as NAT-PM-DC840 or NAT-PM-AC600, for N+1 configurations.

Software Support and Updates
Apart from the Java GUI NATview the NAT-MCH-PHYS80 also supports external management solutions which are based on the Remote Management Control Protocol (RMCP), such as the open-source tool ipmitool. Furthermore, using the NAT-MIB the NAT-MCH-PHYS80 can also be integrated into environments based on the Simple Network Management Protocol (SNMP). The NAT-MCH-PHYS80 can be configured using either uploadable text based script files or via the integrated web interfaces using a standard web browser. Finally, the integrated debug and configuration facilities can be accessed via a serial console or using Telnet. Customers registering for the firmware update service are automatically notified by e-mail when a new firmware version becomes available.

Family of MCH products
The NAT-MCH-PHYS80 is a member of the NAT-MCH family of MCHs which consists of:


  • Particle accelerators
  • Synchrotron experiments
  • Colliding beam accelerators
  • Neutrino oscillation
  • Plasma control
  • Fusion research

Key features
Technical details
Block diagram
Order code
The NAT-MCH-PHYS80 is a powerful management and data switching entity for all MicroTCA.4 systems targeting PCIe-based applications with a need for high-bandwidth and uplinks:
  • Management for
    • 12 AMCs + optional AMC13 in 2nd MCH slot
    • Front and rear cooling units
    • 4 power modules including N+1 redundancy
    • Update channel to secondary MCH
    • 4 eRTMs and 2 rear power modules via LLRF backplane
  • Support for MCH rear transition modules, i.e. NAT-MCH-RTM-RF, NAT-MCH-RTM-RF-COMex-i7 and NAT-MCH-RTM-RF-COMex-i7Q
  • GigaBit Ethernet switching (Fabric A)
  • PCI Express (Gen3) switching (Fabrics D-G)
  • Front panel uplinks
    • 2x 1GbE (load sharing supported)
    • 2x PCIe x8 or 1x PCIe x16 optical uplinks
    • 2x SMA for external CLK support (bi-directional)
    • Serial (RS232) and USB console
  • Clock generation and distribution by special clock module for Physics (NAT-MCH-CLK-PHYS)
  • Configuration options
    • Console (USB, RS232 or Telnet)
    • Script File
    • Web browser 
  • Host based Java GUI for any operating system capable of executing Oracle Java Run-Time Environment (JRE) v1.7 or higher, i.e. Linux, Mac OS-X or Windows
CPU and memory
  • NXP (Freescale) ColdFire MCF54452 CPU @ 266MHz
  • DDR2 RAM: 32/64MB
  • FLASH: 16/32/64MB

IPMI and Compliance

  • 13 AMCs
  • 2 front and 2 rear cooling units
  • 1-4 power modules incl. N+1 redundnacy
  • PICMG 2.9
  • Update to 2nd MCH

Supported Fabrics and Compliance

Fabric A: Gigabit Ethernet

  • 12 AMCs + optional AMC13 in 2nd MCH slot
  • PICMG AMC.2 R1.0
  • PICMG SFP.1 R1.0

Fabric D-G:

  • PCI Express Gen 3 
    • x1 or x4 to 12 AMCs
    • One x16 or two x8 to optical uplink (optional)
    • x16 to RTM or to one AMC slot (requires backplane support)
  • PICMG AMC.1 R1.0

Clock Distribution
NAT-MCH-CLK-PHYS (click for more information)
  • CLK1 and CLK2 by special low jitter and low latency circuitry (NAT-MCH-CLK-PHYS)
  • CLK3  fixed mean 100MHz PCIe clock (HCSL)

Carrier Manager

  • Management of up to 13 AMCs, 4 cooling units and 1-4 power modules
  • Management of 4 eRTMs and 2 rear power modules via LLRF backplane
  • Supports redundant architectures and fail-over procedure
  • Support configurable emergency shutdown of AMCs or entire system

Shelf and System Manager

  • For detached or stand-alone operation both managers are available on-board, hook-in for external managers via 1GbE port at front panel

Operating System and API

  • O/S: OK1
  • API: HPI compliant

Indicator LEDs

  • 3 standard AMC LEDs
  • 12 bi-color LEDs for AMC slot stati
  • 2 bi-color LEDs for cooling units
  • 4 bi-color LEDs for power modules
  • 13 bi-color LEDs for PCIe link status (failed, Gen1, Gen2 or Gen3)

Front Panel Connectors

  • 2x 1GbE for management connection and Fabric A system up-link (load sharing supported)
  • External clock reference (bi-directional)
  • Serial and USB console connectors
  • Fabric D-G uplink (two x8 or one x16) 


Rev #
Date Last Modified
nat_mch_ds Data sheet and NAT-MCH family overview pdf 1.179 KB 1.4 06-07-2012
nat_mch_man_usr NAT-MCH Users Manual pdf 2.9 MB 1.31 26-08-2016
nat_mch_ethx_man_usr User's Manual for 1G/10G Ethernet Switches   pdf  3.0 MB   2.1 12-10-2015 
nat_mch_m4_v1x_man_hw  Hardware Manual for base board v1.x pdf  1.0 MB  1.2  30-06-2014
nat_mch_clk_v41_man_hw    Hardware Manual for CLK module v4.x pdf  904 KB   1.3  30-06-2014
   Hardware Manual for CLK module PHYS pdf  969 KB   1.3 30-06-2014 
nat_mch_pciex80_v1x_man_hw Hardware Manual for PCIexpress x80 hub v1.x pdf  1.2 MB  1.0 01-04-2016

For further documentation on the NAT-MCH (i.e. technical reference manuals) please contact us using the contact form. Thank you.

NAT-MCH-PHYS80 block diagram

Product Code: NAT-MCH - [Options]

-PHYS80 double-width full-size MCH for MTCA.4 applications -
-PHYS80-UPLNK like -PHYS80 with additonal optical uplinks (either two x8 or one x16) for PCIe
-RTM-UPLNK double-width full-size Rear Transition Module providing one copper uplink (x16) for PCIe -PHYS
-RTM-RF double-width full-size Rear Transition Module providing management for LLRF backplane and mounting slot for type-6 COMExpress module -PHYS
-RTM-RF-COMex-i7 like -RTM-RF with mounted Intel® Core™ i7 Ivy Bridge ComExpress module dual core
-RTM-RF-COMex-i7Q like -RTM-RF with mounted Intel® Core™ i7 Ivy Bridge ComExpress module quad core (requires LLRF backplane)


  fibre uplink cable for PCIe uplink -
  PCIe card terminating PCIe uplink -


NATView Java based GUI (Graphical User Interface) for monitoring and control of MTCA systems. 2.25 26-08-2016
- Firmware for NAT-MCH, NAT-MCH-PHYS, NAT-MCH-PHYS80 2.18 26-08-2016

Customers registering for the firmware update service will automatically be notified by e-mail when a new firmware version becomes available.