The NPMC-DSP is a DSP based multi-purpose telecommunication resource board in PMC (PCI Mezzanine Card) form factor. It is targeted at Telecom applications with extensive need for voice or data computation. The module is designed to process standard telecom algorithms, i.e. voice and data compression and decompression or DTMF detection and generation. The module is capable of handling individual timeslots within a TDM stream selected from the H.110 backplane. The design is optimized for handling in parallel as many timeslots (TDM data) as possible. The TDM data streams are supplied by a standard H.110 backplane interface located on the PMC multi-purpose I/O connectors.


Beside special DSP cores from N.A.T. Analog Devices and other third parties offer cores for most commonly used applications including
- Multi-Rate Filter
- Convolutional Encoders
- multi rate filter
- QAM, BPSK and QPSK modulation
- Image / Video Processing
- Voice / Data Compression (G722,G728)
in order to name just few.

The NPMC-DSP is highly flexible and thus suitable for any voice/data application in any signalling or VoP solution such as in ISDN, SS7, ATM, VoIP or 3G environments.


The NPMC-DSP is a P1386.1/Draft 2.0 compatible PMC module that can be plugged onto any VME, cPCI or other carrier board offering a PMC extension slot. The PCI-to-local-bus bridge directly interconnects the PCI bus to the local bus and the onboard devices. The PCI interface is PCI Rev. 2.2 compatible (32bit).

Backplane TDM Access

The onboard H.110 bus controller is realized by a highly flexible and progressive FPGA design, incorporated in a Cyclone I FPGA from Altera. It offers access to the backplane TDM bus supporting the complete H.110 bus (PTMC configuration type 5) or the SC Bus subset on the PMC multi-purpose I/O connectors P13/P14.

Thus the onboard DSPs have access to all 32 TDM streams, each being clocked at up to 8MHz and thus providing up to 4096 timelsots of 64kbps bandwitdh each. Due to the FPGA design of the H.110 controller subchanneling or superchanneling is possible as well.

DSP resources

The NPMC-DSP is equipped with eight ADSP-BF535P Blackfin CPUs from Analog Devices, running at a core frequency of 350MHz.
Each of the DSPs has 32MB of individual SDRAM as well as up to 4MB individual FLASH aside to ensure a most felxible and individual utilization of its resources.

Due to its internal design the Blackfin is a very powerful processing engine with 700 MMACs (max.) and 3.5MIPS per TDM channel. Special coding algorithms that are often used in telecom environments, i.e. G.711, are built-in features.

Key features
Technical details
Block diagram
Order code
Relating the key features of the NPMC-DSP please consider the product description above!
PCI Interface and Compliance
  • PCI Rev. 2.2, 33MHz/32bit

H.110 Bus (and subsets thereof)

  • H.110 (PTMC conf. type 5) or SCSA subset, integrated in a Cyclone I FPGA from Altera


  • Eight ADSP-BF535P Blackfin DSP from Analog Devices, 350MHz core frequency, 700 MMACS, 3.5 MIPS per TDM channel


  • 32 MB SDRAM and 1 or 2 MB FLASH per DSP

Indicator LEDs

  • 4 software programmable LEDs and 1 status indicator LED per DSP at the front panel

Host Operating System Support

  • OK-1, VxWorks, LINUX, dependant on application
  Power Consumption
  • 3.3V 0.8A (typ.) 5V 1.0A (typ.)

  • Temperature (operating): 0ºC to +60ºC with forced air cooling,
  • Temperature (storage): -40ºC to +85ºC
  • Relative Humidity: 10% to 90% at +55ºC (non-condensing)

Standard Compliance

  • P1386 and P1386.1/Draft 2.a
  • PICMG 2.15 configuration type 5


  • voice and data compression and deflating
  • voice and data encryption and decryption
  • DTMF detection and generation
  • VoP
  • special handling of signalling protocols (i.e. SS7, 3G TFO, etc.)
Rev #
Date Last Modified
NPMC-DSP_datasheet PMC-DSP Data Sheet pdf 908 KB 1.3 06-07-2015
NPMC-DSP_manual NPMC-DSP Users Manual pdf 576 KB 1.2 12-11-2010

NPMC-DSP block diagram

Product Code: NPMC - [Option]

-ADSP 8xADSP-BF535P (350MHz), 32MB SDRAM and 1MB FLASH per DSP, H.110 (PTMC type 5) -
-TIDSP-4-0 PMC board with 4x TMS320C6416 (1 GHz) and 0x TMS320C6415 , front panel connector, clock interface -
-TIDSP-5-0 PMC board with 5x TMS320C6416 (1 GHz) and 0x TMS320C6415 , front panel connector, clock interface -


Rev #
Date Last Modified Source level Operating system independant driver development kit  0.1 10-09-2005