NPMC-8280-4E1/T1/J1

Overview

The NPMC-8280-4E1/T1/J1 is a telecommunications interface board in PMC (PCI mezzanine card) form-factor. Based on the Motorola MPC8280 "PowerQuicc II" CPU the NPMC-8280-4E1/T1/J1 is targeted at telecom applications with a need for a powerful and versatile platform, such as applications using SS7, ISDN, ATM, VoP or any combination of these protocols.


Hardware

The NPMC-8280-4E1/T1/J1 is a P1386.1/Draft 2.0 compatible PMC module that can be plugged onto any VME, cPCI or other carrier board offering a PMC extension slot. Using the on-chip PCI bridge of the MPC8280, the NPMC-8280-4E1/T1/J1 is PCI Rev. 2.2 compatible. The MPC8280 PowerQUICC II processor provides computing resources up to 855 MIPS (450MHz). For less demanding applications the MPC8280 can be replaced by the pin-compatible MPC8265.
The four primary rate line interfaces (E1/T1/J1) are driven using Infineon PEB22554 "Quad Falc" framer, and are available on two standard RJ-45 connectors on the front panel.
In addition to the four E1/T1 lines the NPMC-8280-4E1/T1/J1 offers a RS232 serial interface on a mini SUB-D connector and a 10/100 Megabit/sec (10/100BaseT) Ethernet interface on a RJ45 connector to be used with a standard CAT5 UTP cable.
Thus the NPMC-8280-4E1/T1/J1 is the generic platform for any implementation switching between the classic TDM streams as on E1/T1/J1 and the new generation of packetized data applications running on Ethernet.
Moreover, the 100BaseT port can serve as a configuration and management port, i.e. for SNMP.
The onboard FPGA based H.110 bus controller offers access to the H.110 TDM (Time Division Multiplex) bus and its SC Bus subset on the PMC P14 multi-purpose I/O connector.
Equipped with up to 256MB SDRAM and either 16 or 32MB onboard erasable Flash-Memory the NPMC-8280-4E1/T1/J1 is optimized to meet the performance and memory requirements of state-of-the art communication protocols and applications.


Firmware

Communication protocols like SS7, ISDN, etc., are available as binary firmware images as well as operating system independent source code licenses. By default these firmware protocols run on the well proven N.A.T. real-time kernel OK-1, which is optionally available in source code. 
As well as standard protocols N.A.T. offers customized firmware development.
Enhanced software development and effective debugging is supported by the onboard BDM/JTAG interface.